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Von NeuMann MODEL In Computer Architecture

A typical uniporcessor computer system consisting of a memory unit, the ALU, the control unit & the I/O unit.

• The memory unit a single port device consisting of a "Memory Address Register"- (MAR) and a Memory Buffer Register (MBR) also called a Memory Data Register (MDR)

• The memory cells are arranged in the form of several memory words, where each words, that can be Read or Written.

• All the read and write operations on the memory utilize the memory port.

• The ALU performs the arithmetic and logic operations on the data items in the Accumulator(ACC) and /or MBR and typically the ACC retains the results of such operations.

• The control unit consists of a program counter(PC) that contains the address of the instructions to be fetched and an Instruction Register(IP) into which instructions are fetched from the memory for execution.

• Register1 and Register 2 are used to hold the data and address values during computation.

• For Simplicity , the I/O subsystems shown to input and output from the ALU system. In practice, the I/O may also occur directly between the memory and I/O devices without utilizing any processor registers.

• In practice, the I/O and other components of the system are interconnected by a multibus structure on which the data and address flow. Control Unit manages this flow through the use of a appropriate control signals.

This Architecture runs programs in what is know as the Von-NueMann Execution Cycle (also called 'fetch-decode-execution-cycle'), which describes how the machine works.

• The CPU fetches the next program instruction from the memory using the program counter to determine where the instruction is located.

• instruction is decoded into a language the ALU can understand.

• Any data operand required to execute the instruction are fetched from memory and placed in to registers with the CPU i.e IR.

• the ALU executes the instruction and places the results in registers or memory.